|
Lundstrom Purdue, EE-612 Fall 2006 1
Basic Information on Gate Oxides
Information provided by M.A. Alam, Purdue University
August 15, 2006
1) Basic oxidation conditions
In the US, most companies use dry thermal oxidation followed by N2 plasma deposition
and anneal (for leading edge logic transistors). In Japan, there are still few companies
making/using tools that do wet oxidation for relatively thicker oxides ( > 2.0 nm).
2) Oxidation time, temperature, ambient
a) Plasma Nitrides: Oxidation in pure O2 creates the initial film (T = 950 – 1000C),
then N2 is deposited as plasma, and then a rapid thermal anneal (RTA) for 15 sec
drives the N2 down to create the final plasma nitrided film. Good interface,
excellent blockages of Boron penetration, but plasma tools are somewhat
expensive.
b) Thermal Nitrides: NO, NO2, or NH4 is mixed with O2 during growth (T~900 -
1000 C) to create uniform nitrided films. Inexpensive, but may have a lot of N2
related bulk traps. The interface is not as good as plasma nitrided oxides.
3) Properties of resulting oxynitride
10-15% N 2 for Plasma nitrides (N2 added at the end with Plasma deposition, followed by
rapid thermal anneal, RTA)
15-25% N 2 for Thermal oxides (N2 added during growth)
4) The approximate relative dielectric constant
3.9 for pure oxide
~4.6 for 15% N 2 with plasma
("Thermal Nitrides" may have slightly larger value for the same composition.)
5) The approximate, fixed, interface state density, Q F, per cm2
~ 5x10 10 cm-2
6) Effect of N 2 on reliability and mobility
N 2 degrades reliability tremendously and is one of the major causes of negative-bias
temperature instability (NBTI). N2 is used to reduce NMOS leakage (a poor man's "highk")
and prevent Boron penetration from poly gate to the substrate in PMOS. Both
Lundstrom Purdue, EE-612 Fall 2006 2
mobility and reliability are degraded.
7) Current research
a) Oxide scaling has stopped at ~1.2 nm for most companies for 2-3 generations now
(due to leakage). Hence the emphasis on strained devices to improve performance.
b) Introduction of high-k for high-performance logic has been postponed at least to 32
nm node. It is not clear, it will ever get into production, however several Japanese
companies have already included them in low-power products.
c) Engineering the N2 profile (high on the poly-oxide and lower on oxide/Si interface)
is an active area of research (reduces leakage and prevents Boron penetration
without loss of reliability and mobility.
d) Among the reliability issues: Bias temperature instability, gate dielectric
breakdown, and hot carrier degradation -- in that order, define operating voltages.
|