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Digital Circuits - Sample Qns.............

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Printed Date: 10Feb2025 at 2:30am


Topic: Digital Circuits - Sample Qns.............
Posted By: Arpita
Subject: Digital Circuits - Sample Qns.............
Date Posted: 13Feb2007 at 5:42pm



Que. 1 The number of bits needed to encode all letters (26),10 symbols and all
numbers (10) is
A         5
B         7
C         6
D         8

Que. 2     The use of a cache in a computer system increases the
A         available memory space for the program
B         available memory space for data
C         avrage speed of memory acces
D         addressing range of CPU

Que. 3     A  microprocessor has 24 address lines and 32 data lines if it uses 10-bits
of op-code the size of its memory buffer register is
A         22 bits
B         24 bits
C         32 bits
D         14 bits

Que. 4     Schottky damping is resosted to in TTL gates
A         to reduce propogation delay
B         to increases the noise margin
C         to increase the packing margin
D         to increase fan-out

Que. 5     A pulse train can be delayed by a finite number periods using of clock
A         a serial-in-serial out shift resistor
B         a serial -in parallel out shift resistor
C         a parallel -in series out shift resistor
D         a serial -in parallel shift resistor

Que. 6     The switching speed of ECL is very high,because
A         the transistors are switched between cutoff and saturation regions
B         the transistors are switched between active and saturation regions
C         the transistors are switched between active and cutoff regions
D         the transistors may be operated in three regions

Que. 7     The number of comparators in a parallel conversion type 8-bit A to D converter
is
A         8
B         16
C         255
D         256

Que. 8     A dynamic RAM cell which holds 5v has to be refreshed every 20m secs,
so that the stored voltage does not fall by more than 0.5v. if the cell
has a constant discharge current of 0.1pA the storage capacitance of the
cell is
A         4*10^-6F
B         4*10^-9 F
C         4*10^-12F
D         4*10^-15F

Que. 9     The minimized from of the logical expression  (ABC+ABD+ABC+ABC)
A         AC+BC+AB
             _ _  _
B         AC+BC+AB
            _  _  _
C         AC+BC+AB
             _ _   _
D         AC+BC+AB

Que. 10     For a binary half-subtractor having two inputs A and B the correct set
of logical expression for the output D(=A minus) and X(=barrow) are
A         D=AB+AB, X=AB
              _   _  _     _
B         D=AB+AB+AB, X=AB
              _   _    _
C         D=AB+AB, X=AB
                 __     _
D         D=AB+AB, X=AB


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