| Que. 1 |
Signal flow graph is used to find |
| A |
|
stability of the system |
| B |
|
controllability of the system |
| C |
|
transfer function of the system |
| D |
|
poles of the system |
|
| Que. 2 |
The transfer function of a linear system is the |
| A |
|
ratio of the output Vo(t) and input V1(t) |
| B |
|
ratio ofthe derivatives of the output and the input |
| C |
|
ratio ofthe laplace transform of the output and that of the
input with all initial conditions zero |
| D |
|
none of these |
|
| Que. 3 |
The transfer function of a tachometer is of the form |
| A |
|
Ks |
| B |
|
K/s |
| C |
|
K/s+1 |
| D |
|
K/[s(s+1)] |
|
| Que. 4 |
consider a unity feedback control system with open-loop transfer function
G(s)=K/[s(s+1)] thesteady state error of the system due to a unit step
input is |
| A |
|
0 |
| B |
|
K |
| C |
|
1/K |
| D |
|
infinity |
|
| Que. 5 |
The transfer function of a zero order hold system is |
| A |
|
(1/s)(1+e^-st) |
| B |
|
(1/s)(1-e^-st) |
| C |
|
1-(1/s)e^-st |
| D |
|
1+(1/s)e^-st |
|
| Que. 6 |
Consider the feedback control system with loop transfer function G(s)H(s)=K(1+.5s)/s(1+s)(1+2s) |
| A |
|
0 |
| B |
|
1 |
| C |
|
2 |
| D |
|
3 |
|
| Que. 7 |
non minimum phase transfer function is defined as the transfer function |
| A |
|
which has zeros in right half S plane |
| B |
|
which has zeros only in left half S plane |
| C |
|
which has poles in right half S plane |
| D |
|
which has poles in left half S plane |
|
| Que. 8 |
Consider a unity feedback control system with open loop transfer function
G(s)= k/[s(s+1)].the steady state error of the system due to a
unit step input is |
| A |
|
0 |
| B |
|
K |
| C |
|
1/K |
| D |
|
infinite |
|
| Que. 9 |
The transfer function of a phase lead controller is [1+3Ts]/[1+Ts] the
maximum value of phase provided by the controller is |
| A |
|
90 degree |
| B |
|
60 degree |
| C |
|
45 degree |
| D |
|
30 degree |
|
| Que. 10 |
A memory system of size 26kbytes is required to be designed using memory
chips which have 12 address lines and 4 data lines each. the number of
such chips required to design the memory system is |
| A |
|
2 |
| B |
|
4 |
| C |
|
8 |
| D |
|
16 |