Print Page | Close Window

GATE-2000 CSE paper

Printed From: One Stop GATE
Category: GATE Previous Years Test Papers - Discuss Here
Forum Name: CS Papers
Forum Discription: Computer Science Previous Year GATE Papers to can discussed here.
URL: http://forum.onestopgate.com/forum_posts.asp?TID=71
Printed Date: 06Feb2025 at 4:11pm


Topic: GATE-2000 CSE paper
Posted By: Neha Agarwal
Subject: GATE-2000 CSE paper
Date Posted: 05Jan2007 at 5:14pm


1.1 The minimum number of cards to be dealt from an arbitrarily shuffled deck of 52 cards to guarantee that three cards are from some same suit is

  • 3
  • 8
  • 9
  • 12

 

1.2 An n x n array v is defined as follows:

v [i, j] = i-j for all i, j, 1 £ i £ n, 1 £ j £ n

The sum of the elements of the array v is

  • 0
  • n-1
  • n 2 - 3n + 2
  • n 2 (n + 1) /2

 

1.3 The determinant of the matrix is

  • 4
  • 0
  • 5
  • 20

 

1.4 Let S and T be languages over S = {a, b} represented by the regular expressions (a + b *) * and (a + b) *, respectively. Which of the following is true?

  • S Ì T
  • T Ì S
  • S = T
  • S Ç T = f

 

1.5 Let L denotes the language generated by the grammar S ® 0S0/00.

Which of the following is true?

  • L = 0 +
  • L is regular but not 0 +
  • L is context free but not regular
  • L is not context free

 

1.6 The number 43 in 2's complement representation is

  • 01010101
  • 11010101
  • 00101011
  • 10101011

 

1.7 To put the 8085 microprocessor in the wait state

  • lower the-HOLD input
  • lower the READY input
  • raise the HOLD input
  • raise the READY input

 

1.8 Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non­ pipelined but identical CPU, we can say that

  • T1 £ T2
  • T1 ³ T2
  • T1< T2
  • T1 is T2 plus the time taken for one instruction fetch cycle

 

1.9 The 8085 microprocessor responds to the presence of an interrupt

  • as soon as the TRAP pin becomes 'high'
  • by checking the TRAP pin for 'high' status at the end of each instruction fetch
  • by checking the TRAP pin for 'high' status at the end of the execution of each instruction
  • by Checking the TRAP pin for 'high' status at regular intervals

 

1.10 The most appropriate matching for the following pairs

X: Indirect addressing 1 : Loops

Y: Immediate addressing 2 : Pointers

Z: Auto decrement addressing 3: Constants

is

 

  • X-3, Y-2, Z-1
  • X-I, Y-3, Z-2
  • X-2, Y-3, Z-1
  • X-3, Y-l, Z-2

 

1.11 The following C declarations

struct node {

int i;

float j ;

};

struct node *s[10] ;

define s to be

(a) An array, each element of which is a pointer to a structure of type node

(b) A structure of 2 fields, each field being a pointer to an array of 10 elements

(c) A structure of 3 fields: an integer, a float, and an array of 10 elements

(d) An array, each element of which is a structure of type node

 

1.12 The most appropriate matching for the following pairs

X: m = malloc (5); m=NULL; 1 : using dangling pointers

Y: free (n) ; n-> value=5; 2 : using uninitialized pointers

Z: char *p; *p = 'a' ; 3 : lost memory

is

  • X-I, Y-3, Z-2
  • X-2, Y-l, Z-3
  • X-3, Y-2, Z-l
  • X-3, Y-l, Z-2

 

1.13 The most appropriate matching for the following pairs

X: depth first search 1: heap

Y: breadth-first search 2: queue

Z: sorting 3: stack

is

  • ,X-l,Y-2; Z-3
  • X-3, Y-l, Z-2
  • X-3, Y-2, Z-l
  • X-2, Y-3, Z-l



-------------
For more papers visit:
http://onestopgate.com/gate-preparation// - http://onestopgate.com/gate-preparation//



Print Page | Close Window