| Que.
1 |
Comparing the time T1 taken for a single instruction on a pipelined CPU
with time T2 taken on a non pipelined but identical CPU, we can say that |
| A |
|
T1
|
| B |
|
T1>=T2 |
| C |
|
T1< T2 |
| D |
|
T1 is T2 plus the time taken for one instruction fetch cycle |
|
| Que.
2 |
Consider the values A = Ques0 x 10 30, B =-Ques0 x 10 30 , C= 1.0, and
the sequence X: =A+B Y: =A+C X: = X + C Y: =Y+B executed on a computer
where floating-point numbers are represented with 32 bits. The values
for X and Y will be |
| A |
|
X = 1.0, Y =1.0 |
| B |
|
X = 1.0, Y = 0.0 |
| C |
|
X = 0.0, Y = 1.0 |
| D |
|
X = 0.0, Y = 0.0 |
|
| Que.
3 |
What is the scope of m declared in the main program? |
| A |
|
PARAM,P,Q |
| B |
|
PARAM,P |
| C |
|
PARAM,Q |
| D |
|
P,Q
(E)none of htese |
|
| Que.
4 |
Where does the swap space reside ? |
| A |
|
RAM |
| B |
|
Disk |
| C |
|
ROM |
| D |
|
On-chip cache |
|
| Que.
5 |
Trap is which type of interrupt |
| A |
|
synchronous |
| B |
|
Asynchronous |
| C |
|
Hardware |
| D |
|
software |
|
| Que.
6 |
Assume that each charecter code consist of 8-bits.The number of charecters
that can be transmitted per sec. through an asynchronous serial line
at 2400 band rate,and with two stop bits,is |
| A |
|
109 |
| B |
|
216 |
| C |
|
218 |
| D |
|
219
(E)240 |
|
| Que.
7 |
The value of n,output by the program PARAM is: |
| A |
|
0,because n is a actual perameter that corresponds to x in procedure
Q. |
| B |
|
0,because n is a actual perameter to y in procedure Q. |
| C |
|
1,because n is a actual perameter corresponding to x in procedure Q. |
| D |
|
1,because n is a actual perameter corresponding to y in procedure
Q. (E)none of these |
|
| Que.
8 |
A CPU has two modes - privileged and non-privileged. In order to change
the mode from privileged to non-privileged |
| A |
|
a hardware interrupt is needed |
| B |
|
a software interrupt is needed |
| C |
|
a privileged instruction (which does not generate an interrupt) is needed |
| D |
|
a non-privileged instruction (which does not generate an interrupt) is
needed |
|
| Que.
9 |
The main advantage of interrupt concept is elimination of |
| A |
|
spooling |
| B |
|
pooling |
| C |
|
job scheduling |
| D |
|
blocking the currently running process |
|
| Que.
10 |
Which is non vector interrupt? |
| A |
|
INTR |
| B |
|
TRAP |
| C |
|
RST 6.5 |
| D |
|
RST 7.5 |
|
| Que.
11 |
Which is the most appropriate match for the items in the first column
with the items in the second column ? X Indirect Addressing I. Array
implementation Y Indexed Addressing II. Writing relocatable code Z.
Base Register Addressing III. Passing array as parameter |
| A |
|
(X. III), (Y, I), (Z, II) |
| B |
|
(X, II), (Y, III), (Z, I) |
| C |
|
(X, III), (Y, II), (Z, I) |
| D |
|
(x, I), (Y, III), (Z, II) |
|
| Que.
12 |
The performance of a pipelined processor suffers if |
| A |
|
the pipeline stages have different delays |
| B |
|
consecutive instructions are dependent on each other |
| C |
|
the pipeline stages share hardware resources |
| D |
|
all of the above |
|
| Que.
13 |
The minimum number of page frames that must be allocated to a running
process in a virtual memory environment is determined by |
| A |
|
the instruction set architecture |
| B |
|
page size |
| C |
|
physical memory size |
| D |
|
number of processes in memory |
|
| Que.
14 |
A certain processor supports only the immediate and the direct addressing
mods.Which of the following programming language features cannot be implemented
on this processor? |
| A |
|
pointers |
| B |
|
array |
| C |
|
records |
| D |
|
all of these |
|
| Que.
15 |
Ques Let m [0]….m [4] be mutexes (binary semaphores) and P [0] ... P [4]
be processes. Suppose each process P executes the following : wait
(m ); wait (m [(i + 1) mode 4]); …….. release (m ) ; release (m[(i
+ 1) mod 4 ] ); This could cause |
| A |
|
Thrashing |
| B |
|
Deadlock |
| C |
|
Starvation, but not deadlock |
| D |
|
None of the above |
|
| Que.
16 |
A single instruction of a clear the lower four bits of the accumulator
in 8085 assembly language is? |
| A |
|
XIR OFH |
| B |
|
ANI FOH |
| C |
|
XIR FOH |
| D |
|
ANI OFH |
|
| Que.
17 |
Which of the following statment is true? |
| A |
|
ROM is read/write memory. |
| B |
|
PC points to the last instruction that was executed. |
| C |
|
stack works on the principle of LIFO |
| D |
|
All instructions affect the flags |
|
| Que.
18 |
In a page segemented scheme of memory management,the segment table
itself must have a page table because |
| A |
|
the segment table is often too large to fit in one page |
| B |
|
Each segment table is spread over a number of pages |
| C |
|
segment table points to page table and not to the physical
location of the segment |
| D |
|
none of these |
|
| Que.
19 |
I/O redirection |
| A |
|
implies changing the name of a file |
| B |
|
can be employed to use an existing file as input file for a program |
| C |
|
implies connection 2 programs through a pipe |
| D |
|
noneof the above |
|
| Que.
20 |
The sequence of two instructions that multiply the contents of the DE
resister pair by 2 and store the result in HL resister pair(in 8085 assembly
language) is |
| A |
|
XCHG and DAD B |
| B |
|
XTHL and DAD H |
| C |
|
PCHL and DAD D |
| D |
|
XCHG and DAD H |
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One Stop GATE Forum : GATE Previous Years Test Papers - Discuss Here : CS Papers
Topic: Computer Hardware sample auestions for GATE Exam
Topic: Computer Hardware sample auestions for GATE Exam
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