1.9) A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
a) Complement of INTA is active
b) HOLD is active
c) READY is active
d) NONE of these

1.10) In 8085 , which of the following modifies the program counter?
e) Only PCHL instruction
f) Only ADD instructions
g) Only JMP and CALL instructions
h) All instructions


2000


1.7) To put the 8085 microprocessor in the wait state
a) lower the HOLD input
b) lower the READY input
c) raise the HOLD input
d) raise the READY input

2.13) A graphics card has on board memory 1 MB. Which of the following modes can the card not support?
e) 1600 * 400 resolution with 256 colours on a 17 inch monitor
f) 1600 * 400 resolution with 16 million colours on a 14 inch monitor
g) 800 * 400 resolution with 16 million colours on a 17 inch monitor
h) 800 * 400 resolution with 256 colours on a 14 inch monitor


1999


1.21) The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
a) O(n^2) b) O(n) c) O(log n) d) O(1)

2.9) Which of the following sets of components is/ are sufficient to implement any arbitrary boolean function?
a) XOR gates, NOT gates
b) 2 to 1 multiplexers
c) AND gates, XOR gates
d) Three input gates that output (A . B) + C for the inputs A, B, C.


1998


1.15) The threshold level for logic 1 in the TTL family is
a) any voltage above 2.5 V
b) any voltage between 0.8 V and 5.0 V
c) any voltage below 5.0 V
d) any voltage below Vcc but above 2.8 V

2.10) The address space of 8086 CPU is
a) one Megabyte
b) 256 Kilobyte
c) 1K Megabytes
d) 64 Kilobytes