One Stop GATE Forum: CSE-2004 CA & NW

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   47.Consider a system with a two-level paging scheme in which a regular memory access takes 150ns, and servicing a page fault takes 8 milliseconds.An average instruction takes 100ns of CPU time, and two memory accesses. The TLB hit ratio is 90% and the page fault rate is one in every 10000 instructions. what is the effective average instruction execution time? 
a) 645ns b)1050ns c) 1215ns d)1230ns 

55. The routing table of a router is 

dest subnet mask interface 
128.75.43.0 255.255.255.0 eth0 
128.75.43.0 255.255.255.128 eth1 
192.12.17.5 255.255.255.255 eth3 
default eth2 

on which interface will the router forward packets addressed to destinations 128.75.43.16 and 192.12.17.10 respcetively? 
a)eth1 and eth2 b)eth0 and eth2 c) eth0 and eth3 d)eth1 and eth3 

If we 128.75.43.16 AND 255.255.255.0 then we will get 128.75.43.0 
if we 128.75.43.16 AND 255.255.255.128 then we will get 128.75.43.0 
which one to consider?? eth0 or eth1 

192.12.17.10 AND 255.255.255.255 then network id is 192.12.17.10. none exists so it takes default. 

63. 
Inst. Operation Instruction Size (in words) 
Mov R1,5000 R1=MEM[5000] 2 
Mov R2(R1) R1=MEM[(R1)] 1 
Add r2,r3 r2=r2+r3 1 
mov 6000,r2 mem[6000]=r2 2 
halt 1 

Consider that the memory is byte addressable with size 32 bits and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the cpu has been halted after executing the halt instruction, the return address (in decimal) saved in the stack will be? 
1007,1020,1024,1028 

I think ans is 1028. 

64. 
register to/from memory transfer = 3cycles 
add with both operands in register = 1 cycle 
instruction fetch and decode = 2 cycles per word 
total number of clock cycles required to execute the progrm is 
a)29 b)24 c)23 d)20 

I think ans is 24 

65. consider a small 2-way set-associative cache memory, consisting of 4 blocks.For choosing the block to be replaced, use the LRU schem.The number of cache misses for the following sequence of block addresses is 8,12,0,12,8? 
a)2 b)3 c)4 d)5 

8,12,0 causes misses ...so ans. is 3. 

please discuss the problems.

Author	Message
Suman Newbie Joined: 03Feb2007 Online Status: Offline Posts: 1	Topic: CSE-2004 CA & NW Posted: 03Feb2007 at 10:17am
	47.Consider a system with a two-level paging scheme in which a regular memory access takes 150ns, and servicing a page fault takes 8 milliseconds.An average instruction takes 100ns of CPU time, and two memory accesses. The TLB hit ratio is 90% and the page fault rate is one in every 10000 instructions. what is the effective average instruction execution time? a) 645ns b)1050ns c) 1215ns d)1230ns 55. The routing table of a router is dest subnet mask interface 128.75.43.0 255.255.255.0 eth0 128.75.43.0 255.255.255.128 eth1 192.12.17.5 255.255.255.255 eth3 default eth2 on which interface will the router forward packets addressed to destinations 128.75.43.16 and 192.12.17.10 respcetively? a)eth1 and eth2 b)eth0 and eth2 c) eth0 and eth3 d)eth1 and eth3 If we 128.75.43.16 AND 255.255.255.0 then we will get 128.75.43.0 if we 128.75.43.16 AND 255.255.255.128 then we will get 128.75.43.0 which one to consider?? eth0 or eth1 192.12.17.10 AND 255.255.255.255 then network id is 192.12.17.10. none exists so it takes default. 63. Inst. Operation Instruction Size (in words) Mov R1,5000 R1=MEM[5000] 2 Mov R2(R1) R1=MEM[(R1)] 1 Add r2,r3 r2=r2+r3 1 mov 6000,r2 mem[6000]=r2 2 halt 1 Consider that the memory is byte addressable with size 32 bits and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the cpu has been halted after executing the halt instruction, the return address (in decimal) saved in the stack will be? 1007,1020,1024,1028 I think ans is 1028. 64. register to/from memory transfer = 3cycles add with both operands in register = 1 cycle instruction fetch and decode = 2 cycles per word total number of clock cycles required to execute the progrm is a)29 b)24 c)23 d)20 I think ans is 24 65. consider a small 2-way set-associative cache memory, consisting of 4 blocks.For choosing the block to be replaced, use the LRU schem.The number of cache misses for the following sequence of block addresses is 8,12,0,12,8? a)2 b)3 c)4 d)5 8,12,0 causes misses ...so ans. is 3. please discuss the problems. Post Resume: Click here to Upload your Resume & Apply for Jobs

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Unit Newbie Joined: 03Feb2007 Online Status: Offline Posts: 1	Posted: 03Feb2007 at 10:47am
	63. Inst. Operation Instruction Size (in words) Mov R1,5000 R1=MEM[5000] 2 Mov R2(R1) R1=MEM[(R1)] 1 Add r2,r3 r2=r2+r3 1 mov 6000,r2 mem[6000]=r2 2 halt 1 Consider that the memory is byte addressable with size 32 bits and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the cpu has been halted after executing the halt instruction, the return address (in decimal) saved in the stack will be? 1007,1020,1024,1028 I think ans is 1028.
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