One Stop GATE Forum: GATE–Sample Questions-Analog Circuit

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   Que. 1      A cascade amplifier stage is equalent to
A         a comman emittor stage followed by a common  base stage
B         a comman base stage followed by a common emittor stage
C         a common base stage followed by an emittor follower
D         an emittor follower stage followed by a common base stage
Que. 2     In order to make Q point independent and varitions B in a transistor amplifier,it 
is   necessary to make
A         R (b)<<  B R(c)
B         (D)R < or =  B R(c)
C         (D)R(b) < or =  B R
D         R(b) < or =  B R(c)
Que. 3     Input resistance of a common base transistor ckt is of the order of
A         0The output resistance of a common base transistor ckt is of 
the order of
B         50-100 ohm
C         100-150 ohm
D         150-200 ohm
Que. 4     The emitter coupled pair of BJTs gives a linear transfer relation between 
the   differential output voltage and input voltage only when the magnitude 
of V(id) is less   alpha times the thermal voltage, where alpha is
A         4
B         3
C         2
D         1
Que. 5     Maximum efficiency of half wave rectifier is
A         33.33%
B         40.6%
C         50%
D         68%
Que. 6     If the input ac is 10Vrms the maximum voltage that will appear across 
the diode of a   half wave rectifier with a capacitor input filter will 
be
A         10v
B         14v
C         20v
D         28v
Que. 7     The three stage cascaded amplifier of identical non-interacting FET common 
source stage   has all over an voltage gain of 1000 and overall bandwidth 
of 25*10^6rad/sec given   g(m) =5mA/v the shunt capacitance of each stage 
is given by
A         20PF
B         10PF
C         3.2PF
D         1.6PF
Que. 8     When a +ve gate voltage is applied to MOSFET it is said to operate in
A         enhancement mode
B         depletion mode
C         conduction mode
D         none of these
Que. 9     the tunned ckt for good stability should have
A         low C
B         low r
C         high Q
D         low L
Que. 10     by varying which one of the following the RR feedback oscillator are usually 
tunned
A         load impedance
B         bras
C         lore
D         none of these
Que. 11     An operational amplifier has a slow rate of 100V/micre sec. for a freq. 
of 10mhz the maximum value of the sine wave output voltage will be
A         100v
B         50/(pi)^v
C         10v
D         5v
Que. 12     the number of flipflop required to build a mod-15 counters is
A         4
B         5
C         6
D         7
Que. 13     The maximum overall efficiency of a transformer coupled class A amplifier 
is
A         78.5%
B         25%
C         50%
D         85%
Que. 14     In an FET as V(GS) is changed from zero to increasing reverse biased the 
value of g(m)
A         increases
B         decreases
C         remain constant
D         falls suddenly to zero
Que. 15     given for an FET g(m)  =95mA/v total capacitance =500pf for a voltage 
gain of -30 the      bandwidth will be
A         100khz
B         630khz
C         3mhz
D         19mhz
Que. 16     for the resonent ckt shows w =10^5,Q=50,R=400 thevalue of C is given by
A         250PF
B         1000PF
C         500PF
D         1.25PF
Que. 17     In a class A amplifierusing a transistor under ideal condition the maximum 
ac power   delivered is 1 watt the maximum transistor dissipation capability 
has to be
A         1watt
B         2watt
C         3watt
D         4watt
Que. 18     two binary signals A and B are compared the output expression when the 
two signals are   equal is given by
A         ab' +a'b
B         ab + (ab)'
C         (ab)'
D         ab
Que. 19     the most widely used universal gate are
A         OR and AND gates
B         NOR and NAND gates
C         NOR and AND gates
D         NAND and OR gates
Que. 20     the microprocessor contains ROM  chip contains?
A         control function
B         airthmatic function
C         instructions to execute data
D         memory function
Que. 21     Carry-look ahead is type ofadder in which
A         inputs to several stages are examined
B         carries are produced simultaneously
C         carries are produced before hand
D         none of these
Que. 22     Logic shift affects
A         odd positions
B         all positions
C         even positions
D         new positions
Que. 23     Programmable logic array uses
A         ROM matrices
B         PROM matrices
C         RAM matrices
D         solo memory
Que. 24     Race condition can be avoided by introducing......... between the flipflop
A         harmonic suppressor
B         deacceleration
C         delay
D         dusting
Que. 25     An amplifier has an open loop gain of 100, an input impadence of 1kohm,and 
an output       impedance of 100ohm.a feedback network with a feedback 
fector of 0.99 is connected to       the amplifier in a voltage series 
fedback mode the new input and output impedance      respectively are
A         10 ohm and 1 ohm
B         10 ohm and 10 kohm
C         100 ohm and 1 ohm
D         100 kohm and 1 kohm
Que. 26     In a twin wire transmisssion line in the air the adjacent voltage maximum 
are at 12.5cm   and 27.5cm the operating freq. is
A         300mhz
B         1Ghz
C         2Ghz
D         6.28Ghz
Que. 27     The band width of an N stage tunedamplifire with each stage having a 
 band width of   B, is given by
A         B/n
B         B/(sqrt)n
C         B[(sqrt)2^[1/n]-1
D         B/[(sqrt)(/2^[1/n]-1]
Que. 28     the resolution of a 12-bit D/A convertor using a binary ladder with 10v 
as the full   scale output will be
A         2.44mA
B         3.50mA
C         4.32mA
D         5.12mA
Que. 29     the number of comparetor ckt requires to build a 3-bit simultaneous A/D 
convrtor is
A         7
B         8
C         15
D         16
Que. 30     A magnetic drum of 8 inches diameter has 100 tracks and storage density 
of 200bits/inches    its storage capacity will be
A         502400 bits
B         8402 bits
C         1004800 bits
D         202400 bits
Que. 31     the function of inhabit line in a memory in
A         to write 1 in a core
B         to read 1 in a core
C         to write 0 in a core
D         to stop writing 1 in a core
Que. 32     the storage time of transistor is the part of the
A         turn on time
B         turn off time
C         fall time
D         rise time
Que. 33     if the turn on time of a transistor is decreases its turn on time
A         decreases
B         increases
C         is not affected
D         infinite
Que. 34     for an input pulse train of clock period T,the delay produced by an n 
stage shift   resister
A         (n-1)
B         2n
C         (n+1)T
D         2nT
Que. 35     If the memory chip size is 256*1 bits,then the member of chips required 
to make   up 1k bytes of memory is
A         32
B         24
C         12
D         8
Que. 36     In sign magnitude numbers
A         the leading bit stands for the sign
B         the leading bit is part of the magnitude
C         the leading bit is always zero
D         the leading bit is always
Que. 37     
       what is dule of  X + X'Y =X + Y
A         X + Y = XY
B         X' + XY = XY
C         X(X' + Y) = XY
D         X'(X + Y) = X + Y
Que. 38     The "Pinch off" voltage of a JFET is 0.5 volts. Its "Cut Off" votage is
A         (0.5)^1/2 v
B         2.5 v
C         5.0 v
D         (5.0)^3/2 v
Que. 39     four independent message have bandwidth of 100hz, 200hz, and 400hz,respectively 
each   is sampled at the Nyquist rate and the samples are time division 
multiplexed and   transmitted sample rate is
A         1600
B         800
C         400
D         200
Que. 40     in the CMOS  inventor  1. Both are enchancement Type  2. One transistor 
is N Channel and the other  3. Both are N Channel with one enchancement 
and the other depletion type 4. one is enchancement and the other depletion 
type Of the above 4 statment the only true one are
A         4
B         1 and 2
C         1 and 3
D         none of these

Author	Message
aparna Groupie Joined: 30Apr2007 Online Status: Offline Posts: 70	Topic: GATE–Sample Questions-Analog Circuit Posted: 27Nov2007 at 2:37am
	Que. 1 A cascade amplifier stage is equalent to A a comman emittor stage followed by a common base stage B a comman base stage followed by a common emittor stage C a common base stage followed by an emittor follower D an emittor follower stage followed by a common base stage Que. 2 In order to make Q point independent and varitions B in a transistor amplifier,it is necessary to make A R (b)<< B R(c) B (D)R < or = B R(c) C (D)R(b) < or = B R D R(b) < or = B R(c) Que. 3 Input resistance of a common base transistor ckt is of the order of A 0The output resistance of a common base transistor ckt is of the order of B 50-100 ohm C 100-150 ohm D 150-200 ohm Que. 4 The emitter coupled pair of BJTs gives a linear transfer relation between the differential output voltage and input voltage only when the magnitude of V(id) is less alpha times the thermal voltage, where alpha is A 4 B 3 C 2 D 1 Que. 5 Maximum efficiency of half wave rectifier is A 33.33% B 40.6% C 50% D 68% Que. 6 If the input ac is 10Vrms the maximum voltage that will appear across the diode of a half wave rectifier with a capacitor input filter will be A 10v B 14v C 20v D 28v Que. 7 The three stage cascaded amplifier of identical non-interacting FET common source stage has all over an voltage gain of 1000 and overall bandwidth of 2510^6rad/sec given g(m) =5mA/v the shunt capacitance of each stage is given by A 20PF B 10PF C 3.2PF D 1.6PF Que. 8 When a +ve gate voltage is applied to MOSFET it is said to operate in A enhancement mode B depletion mode C conduction mode D none of these Que. 9 the tunned ckt for good stability should have A low C B low r C high Q D low L Que. 10 by varying which one of the following the RR feedback oscillator are usually tunned A load impedance B bras C lore D none of these Que. 11 An operational amplifier has a slow rate of 100V/micre sec. for a freq. of 10mhz the maximum value of the sine wave output voltage will be A 100v B 50/(pi)^v C 10v D 5v Que. 12 the number of flipflop required to build a mod-15 counters is A 4 B 5 C 6 D 7 Que. 13 The maximum overall efficiency of a transformer coupled class A amplifier is A 78.5% B 25% C 50% D 85% Que. 14 In an FET as V(GS) is changed from zero to increasing reverse biased the value of g(m) A increases B decreases C remain constant D falls suddenly to zero Que. 15 given for an FET g(m) =95mA/v total capacitance =500pf for a voltage gain of -30 the bandwidth will be A 100khz B 630khz C 3mhz D 19mhz Que. 16 for the resonent ckt shows w =10^5,Q=50,R=400 thevalue of C is given by A 250PF B 1000PF C 500PF D 1.25PF Que. 17 In a class A amplifierusing a transistor under ideal condition the maximum ac power delivered is 1 watt the maximum transistor dissipation capability has to be A 1watt B 2watt C 3watt D 4watt Que. 18 two binary signals A and B are compared the output expression when the two signals are equal is given by A ab' +a'b B ab + (ab)' C (ab)' D ab Que. 19 the most widely used universal gate are A OR and AND gates B NOR and NAND gates C NOR and AND gates D NAND and OR gates Que. 20 the microprocessor contains ROM chip contains? A control function B airthmatic function C instructions to execute data D memory function Que. 21 Carry-look ahead is type ofadder in which A inputs to several stages are examined B carries are produced simultaneously C carries are produced before hand D none of these Que. 22 Logic shift affects A odd positions B all positions C even positions D new positions Que. 23 Programmable logic array uses A ROM matrices B PROM matrices C RAM matrices D solo memory Que. 24 Race condition can be avoided by introducing......... between the flipflop A harmonic suppressor B deacceleration C delay D dusting Que. 25 An amplifier has an open loop gain of 100, an input impadence of 1kohm,and an output impedance of 100ohm.a feedback network with a feedback fector of 0.99 is connected to the amplifier in a voltage series fedback mode the new input and output impedance respectively are A 10 ohm and 1 ohm B 10 ohm and 10 kohm C 100 ohm and 1 ohm D 100 kohm and 1 kohm Que. 26 In a twin wire transmisssion line in the air the adjacent voltage maximum are at 12.5cm and 27.5cm the operating freq. is A 300mhz B 1Ghz C 2Ghz D 6.28Ghz Que. 27 The band width of an N stage tunedamplifire with each stage having a band width of B, is given by A B/n B B/(sqrt)n C B[(sqrt)2^[1/n]-1 D B/[(sqrt)(/2^[1/n]-1] Que. 28 the resolution of a 12-bit D/A convertor using a binary ladder with 10v as the full scale output will be A 2.44mA B 3.50mA C 4.32mA D 5.12mA Que. 29 the number of comparetor ckt requires to build a 3-bit simultaneous A/D convrtor is A 7 B 8 C 15 D 16 Que. 30 A magnetic drum of 8 inches diameter has 100 tracks and storage density of 200bits/inches its storage capacity will be A 502400 bits B 8402 bits C 1004800 bits D 202400 bits Que. 31 the function of inhabit line in a memory in A to write 1 in a core B to read 1 in a core C to write 0 in a core D to stop writing 1 in a core Que. 32 the storage time of transistor is the part of the A turn on time B turn off time C fall time D rise time Que. 33 if the turn on time of a transistor is decreases its turn on time A decreases B increases C is not affected D infinite Que. 34 for an input pulse train of clock period T,the delay produced by an n stage shift resister A (n-1) B 2n C (n+1)T D 2nT Que. 35 If the memory chip size is 2561 bits,then the member of chips required to make up 1k bytes of memory is A 32 B 24 C 12 D 8 Que. 36 In sign magnitude numbers A the leading bit stands for the sign B the leading bit is part of the magnitude C the leading bit is always zero D the leading bit is always Que. 37 what is dule of X + X'Y =X + Y A X + Y = XY B X' + XY = XY C X(X' + Y) = XY D X'(X + Y) = X + Y Que. 38 The "Pinch off" voltage of a JFET is 0.5 volts. Its "Cut Off" votage is A (0.5)^1/2 v B 2.5 v C 5.0 v D (5.0)^3/2 v Que. 39 four independent message have bandwidth of 100hz, 200hz, and 400hz,respectively each is sampled at the Nyquist rate and the samples are time division multiplexed and transmitted sample rate is A 1600 B 800 C 400 D 200 Que. 40 in the CMOS inventor 1. Both are enchancement Type 2. One transistor is N Channel and the other 3. Both are N Channel with one enchancement and the other depletion type 4. one is enchancement and the other depletion type Of the above 4 statment the only true one are A 4 B 1 and 2 C 1 and 3 D none of these Post Resume: Click here to Upload your Resume & Apply for Jobs

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